Phase interpolators have many applications in high-speed clocking/timing circuits. One application is in clock and data recovery (CDR). Clock and Data Recovery has applications in the high-speed serial I/O circuits found in field programmable gate arrays (FPGAs), memories, and other integrated circuit devices. Another application is the compensation for differing clock frequencies in two clock domains, either on-chip or inter-chip, by using continuous phase rotation to realize a frequency delta from the incoming clock source. Another application is the clock alignment of two or more clocks.
However, different implementations of phase interpolators can consume different amounts of power and lead to different degrees of phase linearity of an output signal. Waveforms generated by conventional current-integrating phase interpolators are not balanced/differential waveforms, and furthermore may have significant Duty Cycle Distortion (DCD), where the ratio of the time duration of the positive or “high” voltage portion of the pulse to the waveform period is not the desired ratio. Both of these attributes degrade performance of the clock signals, resulting in the need for additional correction circuitry to recover the signal. While Current Mode Logic (CML) phase interpolator solutions may have balanced/differential signaling and have better DCD than the other conventional devices, they require signal conditioning/wave-shaping at the interpolator input and/or output in order to achieve good linearity. More particularly, these CML interpolators mix current into a resistor load or a combined resistor and inductor load, rather than into a capacitor where the current charging of a capacitor is more linear, and therefore provide improved linearity. However, these CML solutions do not scale very well with data rate and incur extra area and wave shaping for broadband operation.
Accordingly, circuits and methods that improve the performance of a phase interpolator are beneficial.